16 segment base address
A physical address obtained from the segment address that acts as a type of reference point. By adding a 0 to the end of the segment address to make a 5-digit address, you can specify an arbitrary physical address every 16 bytes as a segment bases.
2-way set associative
A system used to split the cache memory into groups and place the data currently at a specific address in main memory into the "associated" position in the split-out area of the cache. If the cache is split in two, the system is called "2-way set associative." By using a 2-way set associative system, you can change the contents of one cache while keeping the contents of the other cache intact.
64-bit boundary alignment
A format in which data is partitioned every 64 bits from the low address of memory.
A format in which memory access is partitioned into units of 8 bytes.
active page register
The register that specifies the page position of each bank of RDRAM. The banks of RDRAM are separated into four banks of 1 megabyte each. When using the framebuffer and the Z-Buffer, you use the active page register to store the buffers in separate memory banks. You should do this for faster execution speed.
add-on RAM pak
Add-on RAM is RAM that expands memory storage capacity. Here it refers to the Controller Pak.
address conversion buffer
This buffer holds the address conversion table containing the virtual to physical address conversion information. You can use it to convert from the virtual to physical addresses at a high rate of speed. Usually, address conversion buffer is called TLB (Translation Lookaside Buffer).
address space identifier
The 8-bit value used for expanding the virtual address when you provide the virtual addressing through the TLB (Translation Lookaside Buffer).
A software program that acts independently to perform some task on behalf of the user. The software acts as an agent of the user, conducting the task according to the user's intentions even without detailed instructions.
= Audio Interface. Reads audio data from memory and generates stereo audio signals for output to the audio DAC.
The alignment shows the relationship between the information stored in memory and the memory boundary. The N64 system has a rule that says you must align the memory area to the 16-byte boundary so that it becomes a multiple of a cache line.
When the pixel alpha value is larger than a random dither value, the frame buffer is provisionally overwritten. By doing this, gradations can be placed on surfaces and particle effects can be realized.
= Application Programming Interface. The programming interface composed of functions, commands, and utilities that the operating system supplies for the application program.
application programming interface
The width-to-height ratio of a television screen.
I/O that operates with no relation to the action of the thread requesting the I/O.
atomic primitive mode
The mode you can use to avoid the span buffer coherence problem. But this mode seriously reduces the fill-rate.
Refers to the volume of data that can be transferred per unit of time.
Two different formats for storing data in memory space. The example below shows the two ways the 32 bits of data 0xdeadbeef are stored in memory space. In the little-endian method, data is stored in order from the least significant byte. Conversely, in the big-endian method, data is stored in order from the most significant byte.
The process of packing bits into a form that fits some format.
= Blender. Blends pixels that have been processed in the pipeline with pixels in the frame buffer. Part of the anti-aliasing process on polygon edges, and can also be executed in 2 cycle mode for fog.
The process used to execute a program located in an external memory device. It involves initializing the system at startup and loading the program into main memory.
--> 64-bit boundary alignment
= Block Started by Symbol. A data area where initial values are not defined. Thus, in order to use the Bss section, you must clear the initial values (make them 0). When a CAUSE register interrupt occurs, the cause of the interrupt is stored in this register in order to notify the system.
A sorting method that divides numeric values, which you want to sort, into buckets and then does all sorting in the buckets. If the numeric values are evenly distributed, the process will be extremely fast.
A memory space used for temporary data storage to accommodate for differences in transfer speeds when transferring data between systems.
The amount of data that can be fetched into cache from main memory is determined by the cache size. Cache align is the process by which the units for access to memory space are aligned with this cache size.
The condition in which is conformity is maintained between the contents of cache and the contents of memory.
The cache size.
Calling the next process from the current state and executing it the next time after that.
= Color Combiner. This unit combines texels generated by the TX with step RGBA pixels generated by the RS. It takes two color values from each color source and linearly interpolates them.
One way of resetting the VR4000. When the ColdReset signal is made active while the processor is operating, all clocks are restarted. At this time, memory is cleared.
The part that manages the operation of commands.
The part that analyzes commands.
communication packet log file
In the N64, data is transmitted between hidden threads in packets. This log file contains historical information about these packets.
Rather than compiling with the default settings, these options can be used to indicate additions or changes to functions.
(1) The address and other information about the cause of a CPU exception. (2) Information managed by the OS about thread states and register values when the right of execution has been lost. "thread context" , "context switch".
The name for all the different-colored N64 Controllers. The current family includes six colors: gray, black, green, red, yellow, blue.
The external memory device that fits into the slot on the backside of the N64 Controller. The current device has a capacity of 256 Kbit and can easily used to exchange data.
controller pak file system
The management system for the memory area created by the library so the Controller Pak can be shared among different applications.
controller pak menu
The operation menu for the Controller Pak, which is normally started up when the power to the NINTENDO 64 is turned on while pressing the START button.
The control status register (FCR31), one of the registers in the FPU in the VR4300. This is generally the register for controlling the hardware.
An error that arises when the system tries to read an address that does not exist.
The file containing debug information that is created when a program ends abnormally.
core rendering routine
The interrupt that notifies when the internal counter has reached some final value.
count register cycle number
Central Processing Unit.
CPU count register
CPU instruction cache
= Digital to Analog Converter
data cache line size
The minimum unit of information that can be fetched into cache from main memory.
Source level debugger (dbx) command used in UNIX. The N64 debugger (gvd) supports nearly all dbx commands.
device dependent system interface
The interface that is capable of only low-level (direct) operations, excluding all the functions like naming and buffering that are possible with the device-independent system interface.
A control program used for controlling the peripheral equipment connected to the computer.
device independent system interface
The interface that has common I0 functions (protecting, blocking, and buffering) for various devices. You can operate it without knowing the details about the configuration of the device.
The N64 high-priority thread used for device control. After registering the event, event message queue and message, the device manager controls the execution of I/0 operations sequentially from the input command queue.
direct I/O layer
The action of converting a machine language program into assembler mnemonics. This turns the hard-to-understand machine language program into something easier to grasp. The opposite action is to assemble.
A kind of multiprogramming control, in which the Scheduler allocates the right to use the CPU to the next process.
= Direct Memory Access. Refers to direct data transfers between a device and main memory without intermediation by the CPU. This boosts the efficiency of the CPU, since it can be doing other processes during the data transfer.
DMA length register
double wide gio bus
= Display Processor.
DP command buffer
The buffer that stores the RDP display list.
DRAM matrix stack
dual port interrupt
The act of displaying or printing out the contents of programs and files in order to find problems in programs.
ELF object file
ELF is short for Executable and Linking Format. The ELF object file is the object file used for the creation of an ELF executable form file. By linking this you can create an ELF execution file.
A mechanism or circuit that encodes data.
entry high register
A readable and writable register used to gain access to the highest bit of the built-in TLB. It stores the address of the information that caused an exception if a TLB exception occurs.
entry low 0 and 1 register
A readable and writable register used to gain access to the lowest bit of the built-in TLB. The entry Lo registers hold both the even virtual pages (Lo-0) and the odd virtual pages (Lo-1).
EPI is short for Enhanced PI. Refers to a PI function that can specify which device to access. This enables support for not only conventional game paks, but also 64DD and other new devices.
The exception program counter. It holds the virtual address value of the command that directly caused the exception or the virtual address value of the last branch or the jump command.
The mechanism for managing the occurrence of interrupts and exceptions. The occurrence and the end of interrupts and exceptions in the SP, DP, VI and AI are already defined in the N64 OS.
A flag that indicates the occurrence or the end of an event.
event mail box
The event message queue.
event message queue
The message queue used for notification from the system about thread interrupts and other events. The osSetEventMsg() function provides notification on the system side concerning what message to send to which message queue for any given event.
= event notifier.
--> system fault handler
fault thread context
The act of getting data.
In the interlacing method, a complete image (or frame) on the video screen is produced by first scanning the even-numbered horizontal lines in what is called the first field, and then scanning the odd-numbered lines in the second field.
= First-In, First-Out. A method of processing which gives priority to items first added to the queue.
Transferring data from the CPU's on-chip data cache back to main memory.
A method that allows data from any address in associative memory to be mapped to any location in cache.
Fun controller pak series
A four-character code beginning with "N" that identifies N64 software. The code is completely unique, and the fourth character can be used to identify the country of origin (example: Super Mario 64 = NSMJ).
game preamble code
The code added by makerom to clear the Bss, set the stack pointer and jump to the boot entry routine.
game shop debugger
global data area
A global data region that can be used by all functions, and not just internally by some function.
The microprogram assembled together in the processor for use in the execution of various graphics processes.
graphics (RCP) overrun
The condition where the processing of a graphics task in the RSP is not completed in 1 blank.
A graphics task collects various graphics processes (the graphics display list) together into a series of procedures. It is created by the CPU and processed by the RCP.
A two-dimensional grid of fixed size. This is used to divide a two-dimensional area into small regions. By changing the structure of the grid and by discarding much of the unneeded geometry, processing can be reduced.
grid database structure
The debugger that operates on the developmental workstation in the host and communicates with the emulator board through the dbgif program.
The area of memory that is dynamically allocated to meet the changing needs of the application.
The lowest priority thread. It does nothing except when the other threads are not operating. The N64 operating system hangs if there is no idle thread.
in-circuit debug monitor
A method that directly includes the concluded commands in the main routine without using subroutines.
Refers mainly to such elements as variables and objects that make up the data.
The effective address of the program command.
A cache that temporarily holds the program commands. It improves the performance of the command call.
A timer that sends a signal at each constant interval.
I/O sub system
The core of the operating system, performing such tasks as the allocation of system resources.
The time lag between when an address is input to memory and when data is output.
A tool for linking and editing a number of target programs in order to create one machine-language program. Determines addresses and links run-time libraries, etc.
To locate data in a corresponding way from ROM to main memory, or from main memory to cache, etc.
Messages are used to send and receive information among numerous threads and to control the execution of threads. By sending and receiving threads, a higher-priority thread waiting for a message can be swapped for an executable thread. Threads can use messages to communicate with each other and to synchronize their actions.
message block request
The queue for holding messages. A message queue is specified when a message is sent.
= Memory Interface. Sends pixel data back and forth between memory and frame buffer.
Microprogram instructions put together in the processor (RCP) to control the actions of logic units, registers, control flags, etc. By substituting different microcode you can add and modify functionality.
Hardware that uses microcode to perform processes.
mixed symbol table
A device that can select the necessary item from numerous inputs and make one output.
multi thread view
Refers to the use of a number of waves by a single application.
A safeguard technique: while a device is involved in some I/O process, all other I/O processes regarding that device are excluded.
N64 development board
--> N64 emulator board
N64 development software
N64 emulator board
A board that emulates the NINTENDO 64. It is inserted into the gio bus of an SGI INDY workstation. 16 Mbytes of so-called RAMROM emulate the game pak ROM. Applications created with the INDY can be run by downloading them to this board.
The act of associating a name (identification data) with a device used in a program.
Short for non-maskable interrupt.
non maskable interrupt
The name for a file created in a Controller Pak. Game note.
The three-dimensional expansion of a quad tree.
Processing time that is not directly related to the user program. It is the time used by the operating system to allocate or manage system resources and control processes.
When a number of processes overlap.
A method for executing a large program, in which the program is divided into functional blocks, and parts are overwritten to main memory and executed as necessary.
When an executing process exceeds the prescribed processing time needed for a single process.
page mask register
A register to set the page size (4K, 16K, 64K, 256K, 1M, 4M, 16M) of each TLB (Translation Lookaside Buffer) entry.
A method of making more effective use of memory space by dividing a program into a number of "pages" of appropriate size, and only loading pages when they are needed. This differs from the segment method in that the program is properly divided into blocks of fixed size. This makes for a higher memory space utilization rate, but it is harder for the program to handle.
A program that you insert into an existing program to make additions and/or corrections. Used to fix bugs and add functions.
physical memory mapping
The route used for data transfers between RDRAM and a mass storage device. In the N64 it is an AD16 bus.
The region of address space accessible with the PI.
The handler that manages control information for access to the PI bus.
The device manager for processing all DMA operations involving transfers to and from a mass storage device (game pak ROM, etc.).
A technique that speeds up execution by overlapping processes in the CPU. That is, mixed component elements from various processes are piped in to the CPU continuously from the pipeline. No time is wasted.
The act of taking a data element off the current stack pointer.
position independent code
Code that can be addressed anywhere.
power on reset
--> preemptive system
A system that can interrupt a process that is currently executing in order to give the CPU over to the execution of a process of higher priority.
The interrupt to the CPU that is generated when the N64 reset switch is pushed. When a PreNMI is generated, that means that an NMI will follow in around 0.5 second, so preparations must be made, such as saving the currently executing process.
A program that performs preliminary processing before compilation. This is used to expand functionality without modifying the compiler.
A sequence of commands and data.
A tool for measuring various kinds of performance information, including the number of times each resource is called and executed and the amount of time spent executing.
The act of putting a data element onto the current stack pointer. (The stack has a FIFO structure.)
Where a two-dimensional region is divided into a hierarchical structure comprising grids of different sizes.
The DRAM on the development board that is used in place of game pak ROM during the game development process.
= Reality Co-Processor.
RCP task scheduler
Controls the execution order of tasks processed in the RCP. There are two kinds of tasks: graphics tasks and audio tasks, and the latter have priority of execution. If an audio task arises during the execution of a graphics task, the graphics task is interrupted and execution of the audio task is given priority.
The interrupt utilized internally for communications between the development board and the INDY.
rdb output buffer
The buffer utilized internally for communications between the development board and the INDY.
The port that connects the INDY with the development board.
= Reality Display Processor.
= RAMBUS-DRAM. A type of memory developed by the U.S. company Rambus. RDRAM realizes faster data transfers (maximum of 500 MBps) than conventional DRAM.
real time preemptive
--> preemptive system
region allocation routine
region control header
The request-side thread.
Something used by a thread or a task. For example, the CPU, memory, an I/O device, and the RCP are all resources.
The interrupt process for when a vertical synchronization signal is generated.
rmon debug thread
ROM address space
ROM data which can be viewed in a different location than the original address space (inside the game pak ROM). The result is the same no mater which one is accessed. It has the .n64 extension.
ROM image packer
ROM spec file
The file that describes the segment configuration of objects or unprocessed data files. It is referred to when the ROM image is created.
Round Robin Scheduling
A method of scheduling which pays no attention to priority, where processes are swapped in cyclic order at fixed intervals.
= Rasterizer. Generates the x,y coordinates of pixels and their attributes. The attributes that come out of the RS are: R, G, B, A, Z, S/W, T/W, 1/W, L and pixel.
= Reality Signal Processor.
One of the products in the Fun Controller Pak series. The Rumble Pak fits into the backside of the Controller Pak and creates vibrations during a game, adding an extra touch of realism to the game play. It runs on a pair of AA batteries.
A thread that can be run, or executed.
A thread that is running, or executing.
run time data structure
run time library function
A function that is called from one program and inserted into another executing program to support some operation of that program.
run time performance
A tool for collecting Type0 or compressed MIDI data together in a single file.
The thread that manages the order of execution of numerous threads and the allocation of devices and other system resources.
The manager (thread) that decides the execution order of several threads or the allocation order of system resources.
A program is logically divided up (into functional modules, etc.) and only the necessary segment is loaded in order to make more effective use of memory space. This differs from the paging method, in that it is easier to handle from the program, but the tradeoff is a drop in the memory utilization rate, since the length varies in size.
The RDRAM address for the segment under the current control of the RSP (reality signal processor). The RSP microcode can control 16 segments. The segment address contains the segment ID and the offset, so the physical address is found by adding the segment offset to the base address, which is found by using the segment ID to search the segment base register.
segment base register
A register related to the segment table. It holds the segment base address for a specific segment ID.
--> segment address
The register used for specifying a segment address.
A table used for calculating the physical address of a program that is split into segments.
An integer argument used for controlling the synthesis process in a multitasking system. It is similar to an event flag in that it controls the synthesis by using signals (integer flags) to flag the beginning and ending of processes to ensure that no synchronization problems occur.
Support programs for more efficient use of the system, such as utilities for creating and changing files, library editors for managing libraries, linkage editors and debuggers.
A method for splitting cache memory up into a number of parts and mapping the data in each address in main memory to fixed locations in the divided cache space. When cache is split into two parts, it is called "2-way set associative." When it is split up into as many parts as there are data region blocks, it is called "fully associative."
The model name for the Super Famicon
Notification of start-up.
A method of reordering a collection of data elements according to some specified criterion.
source level debugger
A debugger that can debug a high-level language like C while checking the source code.
= Signal Processor.
span buffer coherency problem
When the same pixel is rendered in two consecutive spans, the second span does not wait for the completion of the first span, and it uses as its frame buffer input a frame buffer value that has not been processed by the first span. The result is that it can read a wrong value, and then return an incorrect value to the frame buffer.
SP segment address
The way the RSP specifies addresses. Each address is comprised of the segment ID (coded in a 3 bit word) and the segment offset. You get the physical address by adding the segment offset to the segment base address obtained with the segment ID.
Temporary memory that has a LIFO (last in first out) structure. You pop the stack to remove a data element and push the stack to add a data element.
Refers to the time when the CPU has to wait, for example when the CPU is accessing RDRAM and there is a cache error.
static data segment
static stack process
A thread that is halted.
Control over boundary-aligned data in memory in such a way that it is read contiguously and concatenated for treatment as a large data block.
= Scalar Unit.
The essential parts taken from the OS system after excluding unnecessary parts for a given specification.
CPU processing time is divided up and allocated to a sequence of executable processes.
The table associating symbols (names) with program and data segments and other information.
I/O that completes within the thread requesting the I/O.
Executing an OS function from the program. Also, the phrase used to indicate each call of an OS function.
system exception handler
--> system fault handler
system execution queue
The queue holding those system threads (from among all the threads making up the system) that are in an executable state.
system fault handler
The system that manages interrupts and other exceptions. In the N64 operating system, when an exception occurs, this handler sends a message to the appropriate message queue after looking up the message queue and message from the corresponding event table.
Threads that control DMA or I/O operations in the same way that device manager threads such as the PI Manager or VI Manager manage devices.
target break point
task header structure
The dynamic list that specifies the RSP's operating procedure.
task waiting queue
= Thread Control Block.
= Texture Filter.
In the N64 OS, a thread is the basic processing unit run in the CPU. Threads function in a preemptive system.
thread control block
= Translation Lookaside Buffer.
The geometric shape.
A situation where if you are going to have this work well, then that other thing is not going to fly.
turbo object state
turbo object state structure
user interaction process
variable TLB page size
The TLB page size can be changed for each entry to be either 4KB, 16KB, 64KB, 256KB, 1MB or 16MB.
vector operation unit
One of the units comprising the RSP. It has eight 16-bit product-sum operator units.
Vertical synchronization of scan lines on the TV screen.
Vertical retrace interrupt
= Video Interface.
Video retrace interval
Vertical retrace interval.
An address in "virtual" memory space beyond the actual physical memory. Supported by the memory management unit. If the called data is in physical memory it is used as-is, but from the point of view of the user, it seems like all one big memory space.
virtual address translation
The process of mapping virtual address space into physical address space.
= Vector Unit.
A thread that is waiting.
Refers to a wave statement defined in the spec file. Segments that have already been defined are registered inside the wave. The segments registered inside the wave can use the same symbol.
--> write back cache(antonym: write-through)
write back cache
The method of at first writing data to cache memory when data is to be loaded, and then writing it back to main memory when cache memory overflows. The method speeds up processing, since it cuts down on the frequency of writing to slower-access main memory. This is also the name for that type of cache memory.
write back caching
--> write back cache