Invalidates CPU instruction cache
#include <ultra64.h> /* os.h */ void osInvalICache(void *vaddr, s32 nbytes);
The MIPS R4300 CPU implements a 16Kbyte direct-mapped instruction cache with a line size of 32bytes. The cache is not synchronized with physical memory and thus cache lines must be invalidated to ensure that old instruction codes are not used when more recent instruction codes exist in physical memory.
osInvalICache function invalidates all instruction cache lines that contain the region [vaddr, vaddr+nbytes- 1]. The given address vaddr must be a CPU virtual address, either direct mapped or mapped via the CPU TLB. If vaddr is not aligned to the cache line boundary, and nbytes is not a multiple of the cache line size, a slightly larger region may be invalidated.
The function is mostly used when new instruction codes are read from mask ROM to memory by way of DMA. In this case, the cache must be invalidated prior to reading by way of DMA.
osInvalICache function does the following operations:
If nbytes < 16384: invalidates instruction cache lines with the region of [vaddr, vaddr+nbytes- 1]
If nbytes >= 16384: invalidates all the instruction cache lines.
osMapTLB, osInvalDCache, osWritebackDCache
04/30/1999 Changed format.
11/05/1999 Retranslated "Description." Added "Additional Description."