The main memory in the system is used in parallel by the R4300 CPU, the RSP microcode engine, the RDP graphics pipeline, and the other I/O interfaces of the RCP. The software is responsible for defining the memory map. Please see Chapter 9, "Basic Memory Management" for additional details.
The N64 CPU can use both physical or virtual addresses. The TLB maps virtual addresses into physical addresses (see NOTE). It is anticipated that programs will mainly use KSEG0 (cached, unmapped) addresses for instructions and data. The RSP hardware uses physical addresses. The microcode imposes a segmented addressing scheme to generate the physical addresses. Bits 24 through 27 of the segmented address are used to index into a 16-entry table to obtain the base address of the segment. The upper 4 bits are masked off. The lower bits are an offset into the segment. This scheme is used to create dynamic RSP task lists easily. The RDP hardware uses physical addresses. The RSP microcode translates the segmented addresses stored in the task list into physical addresses.
NOTE: Depending on address space, there are situations where conversion from virtual to physical address is done without using TLB. For example, mapping method is not used when converting each space address between KSEG0 and KSEG1. In this instance, the physical address is calculated by subtracting the base address from the virtual address.
The N64 CPU has an 8 KB writeback data cache. This means that when the CPU writes a variable, it may not be written to main memory until later. Since the RSP reads the task list directly from main memory, the dynamic portion of the task list must be flushed from the data cache before the RSP starts.
You also need to be careful with DMA operations. The data buffer must be flushed from the cache before the write from memory occurs. The data buffer must be invalidated in the cache before a read into memory occurs. If the cache invalidate does not occur, a write back from the cache may destroy data that has just been transferred into main memory by a read DMA. It is also a good idea to align I/O buffers on the 16-byte data cache line size, to avoid cache line tearing. Tearing occurs when a buffer and an unrelated variable share a cache line. The potential writeback of the variable could destroy data read into the I/O buffer.
Please note the following alignment restrictions:
| Alignment for Main Memory: | 8 byte |
| Alignment for ROM: | 2 byte (see NOTE) |
NOTE: There are some restrictions in direct access to a Game Pak using the PI manager. Please access using the OS functions (osEPiStartDma, osEPiReadIo).