The RSP performs 3D geometric transformations while the RDP pipeline rasterizes the polygon. The RDP consist of several pipeline sub-blocks. There are six major logical RDP blocks: the RS, TX, TF, CC, BL, and MI. The connections between these blocks can be reconfigured to the four cycle types listed in Table 12-1, to perform different rasterization operations.
|The RaSterizer generates pixel coordinates and their attributes' slopes. Pixel coordinates consist of X and Y. Attributes consist of R, G, B, A, Z, S/W, T/W, 1/W, L, pixel coverage.
|The TeXturizing unit contains texture memory and samples the texture, based on which texel represents the pixel being processed in the pipeline.
|The Texture Filter performs a 4-to-1 bilinear filter of 4 texel samples to produce a single bilinear filtered texel.
|The Color Combiner performs general blending of color sources by linearly interpolating between two colors with a coefficient. For example, it may take the filtered texel samples and the shading color (RGBA) and combine them together.
|The BLender (blender) blends the pipeline-processed pixels with the pixels in the frame buffer. The blender can do transparencies and also sophisticated antialiasing operations.
|The Memory Interface performs the actual read/modify/write cycles to and from the frame buffer.
Note: The six RDP blocks (RS, TX, TF, CC, BL, and MI) are purely logical blocks. For example, the hardware implementation of RS consist of several blocks. However, for programming, each can be treated as a single logical block.
The pipeline configuration illustrated in the Figure 12-1 shows how the RDP blocks are connected in one-cycle-per-pixel mode.
|Generates pixel and its attribute covered by the interior of the primitive.
|Generates 4 texels nearest to this pixel in a texture map.
|Bilinear filters 4 texels into 1 texel, or performs step 1 of YUV-to-RGB conversion.
|Combines various colors into a single color, or performs step 2 of YUV-to-RGB conversion.
|Blends the pixel with framebuffer memory pixel, or fogs the pixel for writing to framebuffer.
|Fetches and writes pixels from and to the framebuffer memory.
One-cycle mode fills a fairly high-quality pixel. You can generate pixels that are perspectively corrected, bilinear filtered, modulate/decal textured, transparent, and Z-buffered, at one-cycle-per-pixel peak bandwidth.
Note: Reaching peak bandwidth is difficult. The framebuffer memory is organized in row order. In small triangles, it is rare to have long horizontal runs of pixels on a single scanline. In these cases, the pipeline is often stalled, pending memory access for read or write cycles.
The RDP blocks can be reconfigured into a two-cycle-per-pixel pipeline structure for additional functionality. Figure 12-2 shows the RDP pipeline in 2-cycle mode where one pixel is generated every 2 clocks.
|Generates a pixel and its attribute covered by the interior of the primitive.
|Generates 4 texels nearest to this pixel in a texture map. This can be level X of a mipmap.(The textures prepared in advance with different display quality)
|Generates 4 texels nearest to this pixel in a texture map. This can be level X+1 of a mipmap.
|Bilinear; filters 4 texels into 1 texel.
|Bilinear; filters 4 texels into 1 texel, or step 1 of YUV-to-RGB conversion.
|Combines various colors into a single color, OR linear interpolates the 2 bilinear filtered texels from 2 adjacent levels of a mipmap, OR performs step 2 of YUV-to-RGB conversion.
|Combines various colors into a single color, OR chroma keying (The process which sets a specific color to a transparent as a key and synthesizes more than two images except parts of the specific color.).
|Combines fog color with resultant CC1 color.
|Blends the pipeline pixels with framebuffer memory pixels.
|Read/modify/write color memory.
|Read/modify/write Z memory.
Two-cycles-per-pixel mode contains more features than one-cycle- per-pixel mode. In addition to all of the features of one-cycle mode, two-cycle mode can also do mipmapping and fog.
Note: MI0 and MI1 represent two cycles of the MI that access color and z framebuffer cycles, respectively. This is only a logical representation. The MI does not need to run two cycles to perform color and Z-buffer access. One cycle per pixel mode can also perform color and Z-buffer accesses. The reason for this representation is to show that two MI access cycles are balanced in the two-cycle mode. In one-cycle mode, the pipeline is often stalled at MI, waiting for the framebuffer when accessing both color and z.
These RDP blocks are very flexible and can be configured to do many things. Table 12-4 outlines the typical usage of these blocks for a powerful rasterization pipeline. Study the following sections to understand what attribute state is programmable within each RDP block to master the raster subsystem. Attribute states will be explained in detail later.
For high-performance framebuffer clearing, the RDP has a fill mode, which can fill 64 bits per clock. A programmable RDP color attribute is written into the framebuffer during each 64-bit write cycle. The RDP arithmetic pipeline is largely unused, because the computation cannot keep up with the pixel fill rate. The fill mode is most commonly used for clearing color and Z-buffers.
Note: In fill mode, use the render mode g*DPSetRenderMode(G_RM_NOOP, G_RM_NOOP2) to put the blender into a safe state. Attempting to read Z when in fill mode can cause the RDP pipeline to hang.
For high-performance image-to-image copies, RDP also supports a copy mode that can copy 64 bits or 4 pixels per clock. The RDP texture memory in the TX is just a buffer capable of holding up to 4 KB worth of image pixels. You can load bitmaps into this buffer as well as writing back out to the framebuffer. The is a common bit operation that many 2D graphics hardware systems support. Once again, the RDP arithmetic pipeline is largely unused in copy mode. Please see Section 15.5.4, "Alpha Compare Calculation" for additional information.
Note: In copy mode, use the render mode g*DPSetRenderMode(G_RM_NOOP, G_RM_NOOP2) to put the blender into a safe state.