The Texture Engine takes s/w, t/w, 1/w, and LOD values for a pixel and fetches the onboard texture memory (TMEM: special memory of texture built-in RDP) for the four nearest texels to the screen pixel. The game application can manipulate TX states such as texture image types and formats, how and where to load texture images, and texture sampling attributes.
TX treats the 4 KB on-chip texture memory (TMEM) as general-purpose texture memory. The texture memory is divided into four simultaneous accessible banks, giving output of four texels per clock.
The game application can load various sizes of texture with different formats anywhere in the 4 KB texture map. There are eight texture tile descriptors that describe the location of texture images within the TMEM, the format of this texture, and the sampling parameters. Therefore, you can load many texture maps in the TMEM at one time, but there are only eight tiles that are accessible at any time.
Note: There are some restrictions, depending on texel size and 64-bit alignment within the texture memory. Please see Section 13.11.2 "Alignment" for additional information.
Given the eight texture tiles, you can use two-cycle pipeline mode to cycle TX twice and access eight texels (four from each of two tiles). This functionality, coupled with the use of up to eight texture tiles, allows the TX to perform mipmapping and detailed textures.
Furthermore, there are no explicit restrictions requiring power of two tile-sized decrements for mipmaps. Multi-tile texture map sizes are all independently programmable. Therefore, using these tiles and the color combiner block (please see Section 12.6, "CC - Color Combiner", arithmetic logic can result in many special effects. For example, sliding two different frequency band tiles across a polygon surface while combining them with a blue polygon can give a nice ocean wave effect.
Table 12-10 shows the valid combinations of data types and pixel/texel sizes for the Color and Texture images. For RGBA types, the 16-bit format is 5/5/5/1, and the 32-bit format is 8/8/8/8.
The Intensity Alpha type (IA) replicates the I value on the RGB channels and places the A value on the A channel. The IA 16-bit format is 8/8, the 8-bit format is 4/4, and the 4-bit format is 3/1.
Several steps are necessary to load a texture map into the TMEM. You must block-load the texture map itself and set up the attributes for this tile. There are GBI macros that simplify all these steps into a single macro.
There are two ways of loading textures: block or tile mode. Block mode assumes that the texture map is a contiguous block of texels that represents the whole texture map. Tile mode can lift a subrectangle out of a larger image. The following tables list block and tile mode texture-loading GBI commands respectively.
|Texture DRAM address
|Texture tile width and height in texel space
|clamping/mirroring for s/t axis
|Bit mask for wrapping
G_TX_NOMASK or a number: A wrapping bit mask is represented by (1<<number) - 1.
|Shifts applied to s/t coordinate of each pixel.
This is how you "sample" the lower levels of mipmap.
G_TX_NOLOD or a number: (s or t coord >> number) = s/t to sample other mipmap levels.
|upper left s index of the tile within the texture image
|upper left t
|lower right s
|lower right t
These are some restrictions on the size and placement of CI texture maps within the TMEM. The TMEM is actually partitioned into two halves. Four texels are sampled from the first bank and fed into the second bank for texture/color/index table lookup (TLUT).
Four texels from the texture images are sent from first half banks to the second half banks. The second half banks contain color index palettes. Each color map entry is replicated 4 times for four simultaneous bank lookups. Therefore, 8-bit CI textures all require 2 KB (256 x 64 bits per entry) second half banks to hold the TLUT, while 4-bit CI texture can have up to 16 separate TLUTs.
Note: TLUT must reside on the second half of TMEM; while CI texture cannot reside on the second half of TMEM. Non-CI texture can actually reside on the second half of TMEM in unused TLUT palette/entries.x
|Number of entries in the TLUT. For example, a 4-bit texel TLUT would have 16 entries.
|Where the TLUT goes in TMEM
|Where the TLUT is in DRAM
Software can enable and disable TX to perform the following sampling modes:
With TMEM and tile descriptor states, TX also requires explicit synchronization to render primitives with the proper attribute state. Texture loads after primitive rendering must be preceded by a gsDPLoadSync(), and tile descriptor attribute changes should be preceded by a gsDPTileSync().
Note: If you use the high-level programming macros gsDPLoadTexture* or gsDPLoadTexture*_4b, then you don't need to worry about load and tile syncs. They are embedded in the macro.